1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and semiconductor device fabricated using the same and, more particularly, to a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same.
2. Description of Related Art
Semiconductor devices widely employ a discrete device such as a MOS transistor as a switching device. As the integration density of the semiconductor devices increases, the MOS transistor is gradually being downscaled. Such downscaling leads to a lot of problems, such as a short channel effect (SCE), a drain induced barrier lowering (DIBL) effect, and an increase in junction capacitance. Also, owing to the increased integration of the semiconductor devices, the distance between elements is being shortened, and thus the area available for electrical isolation of the elements is also scaled down. As a result, it becomes difficult to prevent latch-up, which is a form of interference between adjacent elements, using conventional isolation techniques, such as a local oxidation of silicon (LOCOS) process or a trench isolation process.
To overcome these drawbacks, research on applications of a silicon-on-insulator (SOI) substrate has been conducted. The SOI substrate includes an insulating layer interposed between a silicon substrate and a top silicon layer. In forming a MOS transistor on the SOI substrate, the MOS transistor includes source/drain regions and a channel induced therebetween, which are disposed in a top silicon layer that is electrically isolated from the silicon substrate. Accordingly, the MOS transistor can be made to be free from latch-up. Further, when a fully depleted SOI substrate is fabricated by thinning the top silicon layer, the resultant MOS transistor can be improved in swing characteristics and off-current characteristics, which are subthreshold characteristics, and can obtain a high saturation current.
However, since the fabrication of the SOI substrate (especially, the fully depleted SOI substrate) involves forming the top silicon layer to a small thickness of several nm, the source/drain regions disposed in the top silicon layer are likewise reduced in thickness, thus impeding a subsequent silicidation process. As a result, the resultant MOS transistor may suffer from relatively high source/drain series resistance. In order to facilitate the foregoing silicidation process, an elevated source/drain structure can be employed by epitaxially growing a single crystalline silicon layer on the top silicon layer in which the source/drain regions are formed. However, in this case, agglomeration may arise in the top silicon layer formed on the insulating layer during the epitaxial growth of the single crystalline silicon layer.
Meanwhile, a fully depleted SOI MOS transistor for improving problems induced by the silicidation process is disclosed in U.S. Pat. No. 6,084,271 entitled “Transistor with Local Insulator Structure” by Yu et al. According to Yu et al., a local insulating layer is formed in a lower substrate using a LOCOS process, and an upper substrate is bonded onto the lower substrate having the local insulating layer using a wafer bonding process, thereby forming an SOI substrate. Thereafter, a MOS transistor is formed on the upper substrate. In this case, the local insulating layer is formed only under a channel of the MOS transistor but not under source/drain regions, so that the source/drain regions still have a sufficient thickness for a silicidation process. However, it undesirable that the wafer bonding process is required to form the local insulating layer. Also, while the MOS transistor is being formed on the upper substrate, the local insulating layer formed in the lower substrate may be incorrectly aligned With the channel of the MOS transistor.